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rt2660 ? ds2660-00 september 2015 www.richtek.com 1 ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. simplified application circuit 6a, 6v, synchronous step-down converter with refin features ? ? ? ? ? continuous 6a sink or source output current ability and droop design for ddr memory termination applications ? ? ? ? ? low r ds(on) power n-mosfet switches 20m / 10m ? ? ? ? ? input voltage range : 1v to 6v ? ? ? ? ? output adjustable from 0.6v to 2v ? ? ? ? ? current-mode constant on-time control design enables fast transient response ? ? ? ? ? supports all mlcc output capacitor and sp/ poscap with robust loop stabilization ? ? ? ? ? selectable 600khz or 1mhz switching frequency ? ? ? ? ? supports pre-biased start-up ? ? ? ? ? selectable over-current protection ? ? ? ? ? various operation mode selection for different application requirements ? ? ? ? ? external tracking start-up application ? ? ? ? ? enable input control and power good indicator ? ? ? ? ? under-voltage and over-voltage protection applications ? ddr-2/3/4 vtt regulation (1/2v ddq ) for enterprise servers, ethernet switches and routers, global storage, gsm base station, and industrial equipments ? enterprise pol (using precision internal vref) general description the rt2660 in thermally enhanced vqfn-20l 3.5x4 package is a full featured 6v, 6a synchronous step-down dc/dc converter designed specifically for double data rate (ddr) memory termination, which provides a continuous 6a sink and source current and fixed 1/2 ddq at output. the current mode cot architecture with external compensation allows the transient response to be optimized over a wide range of loads and achieves nearly constant switching frequency over line, load, and output voltage ranges. the multiple sets of over-current limit and switching frequency offer an optimized power chain for application design. efficiency is maximized through the integrated 20m / 10m mosfets, and cycle-by-cycle current limit provides protection against shorted outputs. output external tracking function, output soft discharge, power good indicating, output droop support are all featured in the rt2660. in addition, the device is specified from 0 c to 85 c to perform an excellent regulation with an accurate 1% reference voltage over temperature. rt2660 vin c in r1 r2 c ref r comp c comp v in enable mode en mode comp vref refin gnd pgnd pgood v5in vout sw boot l r pgood v out pgood v v5in c out c boot c v5in
2 rt2660 www.richtek.com ds2660-00 september 2015 ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description pin no. pin name pin function 1, 2, 3, 21 (exposed pad) pgnd power ground. provide the ground return path for the low-side power mosfet and positive input of an internal amplifier for current sensing circuit. the exposed pad must be soldered to a large pcb and connected to pgnd for minimum power dissipation. 4, 5 vin power input. supplies the power switches of the device. 6 gnd signal ground. provides the return pat h for control circuitry and internal reference. 7 vref reference output. a specified 2v reference output is supplied by internal linear regulator. decouple with a 0.22 ? f capacitor between this pin and gnd. 8 comp compensation node. the current compar ator threshold increases with this control voltage. connect external compensation elements between this pin and vref pin to stabilize the control loop. 9 refin reference input. the output voltage is targeted by reference input, which is applied from 0.6v to 2v. 10 vout output voltage monitor node. a negative i nput of the gm error amplifier and it is allowed to be a discharge path if any protection is triggered. 11 to 15 sw switch node. sw is the switching node that supplies power to the output and connect the output lc filter from sw to the output load. 16 boot bootstrap supply for high-side gate driver. connect a 100nf or greater capacitor from sw to boot to power the high-side switch. pin configurations vqfn-20l 3.5x4 (top view) pgnd pgnd pgnd vin vin gnd vref comp vout refin sw sw sw sw sw en v5in pgood mode boot pgnd 21 16 20 17 18 19 10 9 8 7 6 11 12 13 14 15 1 2 5 4 3 ordering information note : richtek products are : ? rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ? suitable for use in snpb or pb-free soldering processes. marking information 04= : product code ymdnn : date code rt2660lgqv 05= : product code ymdnn : date code RT2660HGQV rt2660 package type qv : vqfn-20l 3.5x4 (v-type) lead plating system g : green (halogen free and pb free) l : latched ovp and uvp h : ovp non-latch, uvp hiccup 05=ym dnn 04=ym dnn
3 rt2660 ds2660-00 september 2015 www.richtek.com ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram pin no. pin name pin function 17 en enable control input. floating this pin or connecting this pin to logic high can enable the device and connecting this pin to gnd can disable the device. 18 mode mode selection node. there are 8 modes in rt2660. connect the specified resistance to gnd for selecting different modes of switching frequencies, oc limit thresholds, and light-load operations. 19 pgood power good indicator output. this pin is an open-drain logic output that is pulled to ground when the output voltage is lower or higher than its specified threshold under the conditions of ovp, otp, dropout, en shutdown, or during slow start. 20 v5in fixed 5v supply voltage input. supplies the control circuitry and internal reference of the device. + - uv + - ov + - + delay + - + - v refin + 16% v refin - 16% v refin - 30% v refin + 20% ramp comp + - pwm ss dac + - current sense zc threshold modulation + - zc sw on-time selection xcon drvl uvp ovp control logic on/off time minimum on/off skip/oda/fpwm ocl/ovp/uvp discharge vbg + - oc 8r r current sense amplifier drvh t on one- shot discharge comp refin en vref vout gnd pgood mode boot vin sw v5in pgnd vs amplifier 15a
4 rt2660 www.richtek.com ds2660-00 september 2015 ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. operation the rt2660 is a synchronous low voltage step-down converter that can support the v5in range from 4.5v to 5.5v and the output current can be up to 6a. the rt2660 uses a constant on-time, current mode architecture. in steady-state operation, the high-side n-mosfet is turned on when the current feedback reaches comp level which is the amplified difference between the reference voltage and the feedback voltage. the switching frequency of 600khz or 1000khz allows for efficiency and size optimization when selecting the output filter components. the switching frequency is set using the mode pin. the rt2660 reduces the external component count by integrating the boot recharge mosfet. the bias voltage for the integrated high-side mosfet is supplied by a capacitor between the boot and sw pins. the boot capacitor voltage is monitored by an boot detection circuit and turns off the high-side mosfet when the voltage falls below a threshold voltage. the ss pin is used to minimize inrush currents or provide power supply sequencing during power up. a small value capacitor should be coupled to the pin for slow start. the ss pin is discharged before the output power up to ensure a repeatable restart after an over-temperature fault, uvlo fault or disable condition. the error amplifier ea adjusts comp voltage by comparing the output voltage to the refin voltage. when the load increases, it causes a drop in the feedback voltage relative to the reference, then the comp voltage rises to allow higher inductor current to match the load current. bootstrap voltage (boot) and low dropout operation the rt2660 has an integrated boot regulator and requires a small ceramic capacitor between the boot and sw pins to provide the gate drive voltage for the high-side mosfet. the value of the ceramic capacitor should be 0.1 f. a ceramic capacitor with an x7r or x5r grade dielectric with a voltage rating of 10v or higher is recommended because of the stable characteristics over temperature and voltage. when the boot voltage is lower than the threshold voltage, low-side mosfet turns on and built-in bootstrap mosfet will recharge the boot capacitor. the high-side mosfet is always turned off when boot voltage is lower than threshold voltage. pwm frequency and adaptive on-time control the on-time can be roughly estimated by the equation : out on in sw v 1 t = vf ? error amplifier the rt2660 has a transconductance amplifier. the error amplifier compares the v out voltage to the refin voltage the refin voltage can comes from external power source or taps off the voltage divider from the 2v vref. the transconductance of the error amplifier is 1000 a/v during normal operation. the frequency compensation components are placed between the comp pin and ground. auto-zero current detector the auto-zero current detector circuit senses the sw waveform to adjust the zero current threshold voltage. when the current of low-side mosfet decreases to the zero current threshold, the low-side mosfet turns off to prevent negative inductor current. in this way, the zero current threshold can adjust for different conditions to get better efficiency. protection features the rt2660 has many features to protect the device. under-voltage protection (uvlo) the rt2660 continuously monitors the voltage on the v5in pin to ensure that the voltage level is high enough to bias the device properly and to provide sufficient gate drive potential to maintain high efficiency. the converter starts with approximately 4.3v and has a nominal hysteresis of 440mv. if the 5v uvlo limit is reached, the converter transitions the phase node into an off function. and the converter remains in the off state until the device is reset by cycling 5v until the 5v por is reached (2.3v nominal). the power input does not have an uvlo function.
5 rt2660 ds2660-00 september 2015 www.richtek.com ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. power good the rt2660 has one open-drain power good (pgood) pin. the pgood pin de-asserts as soon as the en pin is pulled low or an under-voltage condition on v5in or any other fault is detected. output over-voltage protection (ovp) in addition to the power good function described above, the rt2660 has additional ovp and uvp thresholds and protection circuits. an ovp condition is detected when the output voltage is approximately 120% x v refin . in this case, the converter de-asserts the pgood signals and performs the over- voltage protection function. during ovp, the low-side mosfet is always on before triggering a negative over- current. when a negative oc is also tripped, the low-side mosfet is no longer continuously on, and pulsed signals are generated to limit the negative inductor current. for rt2660l ovp latch mode, when the vout pin voltage drops below 400mv, the low-side mosfet is turned off and the converter latches off. the converter remains in the off state until the device is reset by cycling 5v until the 5v por is reached or when the en pin is toggled off and on. for rt2660h ovp non-latch, when the vout pin voltage drops below 400mv, the low-side mosfet is turned off (non-latch), recovery until the vout pin voltage exceeds 400mv again. output under-voltage protection (uvp) output under-voltage protection works in conjunction with the current protection described in the over-current protection and over-current limit sections. if the output voltage drops below 68% of v refin , after approximately a 256 s delay, the device stops switching and enters uvp. for rt2660l uvp latch mode, the device stop switching and enter latch mode. the converter remain in the off state until the device is reset by vin or en. for rt2660h uvp hiccup mode, the device stops switching and enters hiccup mode. after a hiccup waiting time, a re-start is attempted. if the fault condition is not cleared, hiccup mode operation may continue indefinitely. over-current protection (ocp) both positive and negative over-current protection are provided in the rt2660 : ? over-current limit (ocl) rt2660 has cycle-by-cycle over current limiting protection. the inductor current is monitored during the low-side mosfet turning on. when the inductor current is larger than the over current trip level, the high-side mosfet turns off until the current drops below the ocl limit. because rt2660 uses a valley current limiting scheme, the average output current limit calculation is valley ocl trip level plus half of the inductor ripple current. ? negative ocl the negative ocl circuit acts when the converter is sinking current from the output capacitor(s). the converter continues to act in a valley mode, the absolute value of the negative ocl set point is typically ? 9.3a or ? 7.3a (depending on mode selection). over-temperature protection (otp) the rt2660 has an over-temperature protection. when the device triggers the otp, the device shuts down. until the temperature drops below the low temperature threshold, the otp relieves and the device re-soft starts.
6 rt2660 www.richtek.com ds2660-00 september 2015 ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. electrical characteristics parameter symbol test conditions min typ max unit supply voltage v5in supply input operating voltage v 5in (note 5) 4.5 5 5.5 v vin supply input operating voltage v in (note 5) 1 -- 6 v absolute maximum ratings (note 1) ? supply and boot-to-switch input voltages, v in , v v5in , and (v boot ? v sw ) ---------------------------- ? 0.3v to 7v ? boot pin input voltage, v boot ------------------------------------------------------------------------------------ ? 0.3v to 14v ? switch node input voltage, sw --------------------------------------------------------------------------------- ? 2v to 7v ? switch node, sw (<10ns) ----------------------------------------------------------------------------------------- ? 5v to 10v ? en pin in put v oltage ------------------------------------------------------------------------------------------------ ? 0.3v to 7v ? mode and refin pin input v oltages -------------------------------------------------------------------------- ? 0.3v to 3.6v ? vout pin in put v oltage ------------------------------------------------------------------------------------------- ? 1v to 3.6v ? comp and vref output voltages ----------------------------------------------------------------------------- ? 0.3v to 3.6v ? pgood output voltage ------------------------------------------------------------------------------------------- ? 0.3v to 7v ? pgnd output voltage ---------------------------------------------------------------------------------------------- ? 0.3v to 0.3v ? power dissipation, p d @ t a = 25 c vqfn-20l 3.5x4 ----------------------------------------------------------------------------------------------------- 3.125w ? package thermal resistance (note 2) vqfn-20l 3.5x4, ja ----------------------------------------------------------------------------------------------- 32 c/w vqfn-20l 3.5x4, jc ----------------------------------------------------------------------------------------------- 10 c/w ? lead temperature (soldering, 10 sec.) ------------------------------------ ------------------------------------- 260 c ? junction temperature ----------------------------------------------------------------------------------------------- 150 c ? storage temperature range -------------------------------------------------------------------------------------- ? 65 c to 150 c ? esd susceptibility (note 3) hbm (human body model) ---------------------------------------------------------------------------------------- 2kv cdm (charged device model) ------------------------------------------------------------------------------------ 1kv recommended operating conditions (note 4) ? input supply voltage, v in ------------------------------------------------------------------------------------------ ? 1v to 6v (por) ? boot pin input voltage, v boot ------------------------------------------------------------------------------------ ? 1v to 12.5v (por) ? switch node input voltage, v sw --------------------------------------------------------------------------------- ? 1v to 6.5v ? boot-to-switch input voltage, (v boot ? v sw ) ----------------------------------------------------------------- ? 0.1v to 5.5v (por) ? input logic supply voltage, v v5in ------------------------------------------------------------------------------- 4.5v to 5.5v ? en input voltage, v en ---------------------------------------------------------------------------------------------- ? 0.1v to 5.5v (por) ? pgood output voltage, v pgood -------------------------------------------------------------------------------- ? 1v to 5.5v ? v out , mode, and refin pin input v oltages ------------------------------------------------------------------ ? 1v to 3.5v ? comp and v ref output voltage s ------------------------------------------------------------------------------- ? 1v to 3.5v ? pgnd output voltage ---------------------------------------------------------------------------------------------- ? 1v to 0.1v ? junction temperature range -------------------------------------------------------------------------------------- ? 40 c to 125 c (v in = 5v, pgnd = gnd, t a = ? 40 c to 85 c, unless otherwise specified)
7 rt2660 ds2660-00 september 2015 www.richtek.com ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit v5in quiescent current v en = high -- 1.1 2 ma v5in shutdown current v en = low -- 0.2 7 ? a vin shutdown current -- 0.2 10 v5in under-voltage lockout threshold v 5in_uvlo v en = high, v in rising 4.2 4.37 4.5 v v5in under-voltage lockout threshold hysteresis ? v 5in_uvlo -- 440 -- mv v5in reset threshold ovp latch is reset when v v5in < reset threshold 1.5 2.3 3.1 v enable voltage enable input voltage v ih v en rising 2 -- -- v v il v en falling -- -- 0.5 enable input current -- -- 1 ? a reference voltage vref voltage v vref i vref = 0 ? a 1.98 2 2.02 v i vref = 50 ? a 1.975 2 2.025 vref under-voltage lockout threshold v vref_ uvlo v en = high, v vref rising -- 1.8 -- vref under-voltage lockout hysteresis ? v vref_ uvlo -- 100 -- mv vref sink current v vref = 2.05v -- 2.5 -- ma sw and boot constant on-time v in = 5v, v out = 1.05v, f s = 1mhz (note 5) -- 210 -- ns v in = 5v, v out = 1.05v, f s = 600khz (note 5) -- 310 -- minimum off-time v in = 5v, v out = 1.05v, f s = 1mhz, v out < v refin -- 270 -- internal boot switch on-resistance i boot = 10ma, t a = 25c -- -- 10 ? internal boot switch leakage current v boot = 13v, v sw = 6v -- -- 1 ? a default soft-start soft-start time t ss from v en = high to v out = 95%v refin -- 1.6 -- ms soft-start delay time from v en = high to v out ? 0v -- 260 -- ? s error amplifier and pwm comparator error amplifier trans-conductance gm -- 1 -- ma/v common mode input voltage range v cm (note 5) 0 -- 2 v
8 rt2660 www.richtek.com ds2660-00 september 2015 ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit differential mode input voltage range v dm 0 -- 80 mv error amplifier sinking current v comp = 2v, v out ? v refin = ? 80mv -- 80 -- ? a error amplifier sourcing current v comp = 2v, v out ? v refin = 80mv -- ? 80 -- error amplifier input offset t a = 25 ? c -- 0 -- mv error amplifier ? 3db frequency (note 5) 4.5 6 7.5 mhz zero crossing comp internal offset v zxoff -- 0 -- mv current limit and internal current sense low-side switch sourcing current limit valley detection -- 7.6 -- a low-side switch sinking current limit -- ? 9.3 -- current sense trans- impedance r cs low-side current sensing 43 53 57 m ? power good power good falling threshold v out falling (fault) -- 84 -- %v refin power good rising hysteresis v out rising (good) -- 8 -- power good rising threshold v out rising (fault) -- 116 -- power good falling hysteresis v out falling (good) -- ? 8 -- minimum vin voltage for indicating pgood i pgood sinks 2ma 0.7 0.9 1.1 v power good enable delay time external tracking -- 8 -- ms power good indicating good delay time 0.8 1 1.2 power good indicating fault delay time -- 10 -- ? s power good pull low voltage pgood = fault, v v5in = 4.5v, i pgood sinks 4ma -- -- 0.3 v power good leakage current pgood = good, v pgood = 5.5v ? 1 0 1 ? a vout vout accuracy v refin = 1v, non-droop application ? 1 -- +1 %v refin vout soft discharge resistance -- 42 -- ? over-voltage protection threshold 115 120 125 %v refin
9 rt2660 ds2660-00 september 2015 www.richtek.com ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. guarantee by design. parameter symbol test conditions min typ max unit under-voltage protection threshold device latches off and begins to soft discharge 65 68 71 %v refin over-voltage protection delay time from v out > 120%v refin to ovp trip -- 10 -- ? s under-voltage protection delay time from v out < 68%v refin to uvp trip -- 256 -- under-voltage protection enable delay time from v en = high to uvp enable -- 2 -- ms external tracking application, from v out ? 0v to uvp enable -- 8 -- over-temperature protection thermal shutdown threshold t sd -- 145 -- ? c thermal shutdown hysteresis ? t sd -- 20 -- mode selection mode threshold voltage threshold 1 80 130 180 mv threshold 2 (note 5) 200 250 300 threshold 3 370 420 470 threshold 4 1765 1800 1850 mode input current -- 15 -- ? a
10 rt2660 www.richtek.com ds2660-00 september 2015 ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit table 1. mode definitions mode mode resistance (k ? ) light-load power saving mode switching frequency (f sw ) over current limit (ocl) valley (a) 1 0 skip 600khz 7.6 2 12 600khz 5.4 3 22 1mhz 5.4 4 33 1mhz 7.6 5 47 pwm 600khz 7.6 6 68 600khz 5.4 7 100 1mhz 5.4 8 open 1mhz 7.6 rt2660 vin 4, 5 c in r1 r2 c ref r comp c comp v in 1v to 6v enable mode en 17 mode 18 8 comp 7 vref refin 9 gnd pgnd pgood v5in vout sw boot 6 1, 2, 3, 21 (exposed pad) 19 20 10 11 to 15 16 l r pgood v out 0.6v to 2v pgood v v5in 5v c out c boot c v5in
11 rt2660 ds2660-00 september 2015 www.richtek.com ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics output voltage vs. input voltage 0.57 0.58 0.59 0.60 0.61 0.62 0.63 4.5 4.75 5 5.25 5.5 input voltage (v) output voltage (v) pwm = 1mhz, v pp = 2.5v, v out = 0.603v i out = 0a i out = 100ma i out = 3a i out = 6a output voltage vs. output current 0.585 0.590 0.595 0.600 0.605 0.610 0.615 0123456 output current (a) output voltage (v) v out = 0.603v v in = 2.5v v in = 1.2v current limit vs. v5in 4 5 6 7 8 9 10 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 v5in (v) current limit (a) v out = 0.603v, valley frequency vs. output current 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 output current (a) frequency (mhz) 1 v in = 2.5v, v out = 0.603v, i out = 0a to 6a frequency vs. temperature 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -50 -25 0 25 50 75 100 125 temperature (c) frequency (mhz) 1 v in = 2.5v, v out = 0.603v, f = 1mhz efficiency vs. output current 40 45 50 55 60 65 70 75 80 85 90 95 0123456 output current (a) efficiency (%) v out = 0.603v v in = 2.5v v in = 1.2v
12 rt2660 www.richtek.com ds2660-00 september 2015 ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. en threshold vs. temperature 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -50 -25 0 25 50 75 100 125 temperature (c) en threshold (v) v in = 2.5v, v out = 0.603v, i out = 0a en high level threshold en low level threshold time (1 s/div) output ripple voltage v in = 2.5v, v out = 0.603v, i out = 6a, l = 0.25 h v out (10mv/div) v lx (2v/div) i out (4a/div) time (1 s/div) output ripple voltage v out (10mv/div) v lx (2v/div) i out (4a/div) v in = 2.5v, v out = 0.603v, i out = 3a, l = 0.25 h v in = 2.5v, v out = 0.603v, i out = 0a to 3a, l = 0.25 h time (100 s/div) load transient response v out (20mv/div) i out (2a/div) time (100 s/div) load transient response v out (20mv/div) i out (2a/div) v in = 2.5v, v out = 0.603v, i out = 0a to 6a, l = 0.25 h shutdown current vs. temperature 0 1 2 3 4 5 6 7 -50 -25 0 25 50 75 100 125 temperature (c) shutdown current (a) 1 v in = 2.5v, v out = 0.603v, i out = 0a
13 rt2660 ds2660-00 september 2015 www.richtek.com ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information the rt2660 employs current mode cot architecture that provides ease of use, low external component count and fast transient response. the synchronous buck regulator capable of delivering up to 6a continuous current and set switching frequency up to 1mhz. some feature of current mode cot ? effective bandwidth is very high ? no slope compensation necessary ? double complex zero at half the switching frequency term of fixed frequency peak cm converter disappears. operation of current mode cot referring to figure 1, v comp is the amplified difference between the reference voltage and the feedback voltage. v cs is valley current sense voltage (sensing the inductor current). the pwm comparator senses where the two waveforms cross and triggers the on time generator. t on time (s) t current feedback v cs v comp v ref voltage (v) figure 1. current mode cot waveforms adaptive constant on-time control adaptive on time generator makes the system operate in fixed frequency when v in or v out change. the technique improves cot by making the one-shot on-time proportional to v out and inversely proportional to vin. in this way, an on-time is chosen as approximately what it would be for an ideal fixed-frequency pwm in similar input/output voltage conditions. the on-time calculates equation of the buck converter as shows as follows : out on in sw v t vf ? ? non-droop mode operation the rt2660 can be configured as a non-droop solution. the benefit of a non-droop approach is that load regulation is flat, therefore, in a system where tight dc tolerance is desired, the non-droop approach is recommended. for the intel system agent application, non-droop is recommended as the standard configuration. the non- droop approach can be implemented by connecting a resistor and a capacitor between the comp and the vref pins. the purpose of the type ii compensation is to obtain high dc feedback gain while minimizing the phase delay at unity gain cross over frequency of the converter. the value of the resistor (r c ) can be calculated using the desired unity gain bandwidth of the converter, and the value of the capacitor (c c ) can be calculated by knowing where the zero location is desired. the capacitor c p is optional, but recommended. its appropriate capacitance value can be calculated using the desired pole location. figure 2 shows the basic implementation of the non-droop mode using the rt2660. figure 2. non-droop mode droop mode operation the terminology for droop is the same as load line or voltage positioning as defined in the intel cpu vcore specification. based on the actual tolerance requirement of the application, load-line set points can be defined to maximize either cost savings (by reducing output capacitors) or power reduction benefits. accurate droop voltage response is provided by the finite gain of the droop amplifier. the equation for droop voltage is shown below equation : where f sw is operate frequency. + - + - + - r ds(on) ls rcs vrefin gm + - pwm comparator r c c c c p comp driver vref + - vref vout sw hs ls esr c out r out vin l out + - vref
14 rt2660 www.richtek.com ds2660-00 september 2015 ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. where ? r cs is current sense trans-impedance. ? r droop is the value of resistor from the comp pin to the vref pin. ? gm is the error amplifier trans-conductance. figure 3 shows the basic implementation of the droop mode using the rt2660. out ref r2 vv r1+r2 ?? figure 3. droop mode figure 6. tracking startup timing 600mv 600mv forced ccm operation loop determined operation pgood delay 1ms 260s minimum 9ms en and v5in refin vout pgood rt2660 can be configured for tracking application. when tracking configuration is desired, output voltage is also regulated to the refin voltage which comes from an figure 4. tracking configuration 1 figure 5. tracking configuration 2 non-tracking mode the rt2660 can be configured for non-tracking application. when non-tracking is configured, output voltage is regulated to the refin voltage which taps off the voltage dividers from the 2v reference voltage. either the en pin or the v5in pin can be used to start up the device. the rt2660 uses internal voltage servo dac to provide a 1.6ms soft-start time during soft-start initialization. (see figure 7) in a non-tracking application, the output voltage is determined by the resistive divider between the vref pin and the refin pin. cs out droop droop ri v rgm ? ? ? figure 7. non-tracking condition external power source. in order for the rt2660 to track mode (see figure 6). the valid refin voltage range is between 0.6 v to 2 v. power sequences tracking mode in a tracking application, vddq can be vin or it can be an additional voltage rail. thus, r1 = r2 both in figure 4 and figure 5. figure 8. non-tracking startup timing + - + - + - r ds(on) ls vrefin + - pwm comparator comp driver vref + - vref vout sw hs ls esr c out r out vin l out r droop + - vref rt2660 vin 4, 5 vddq r1 refin 9 r2 rt2660 vin 4, 5 vin r1 refin 9 r2 vddq rt2660 vref 7 r1 refin 9 r2 500mv en and v5in vrefin vout pgood 100s fixed 1.6ms soft-start +16% -16% +8% -8% -5% power good window, reference to refin pgood delay 1ms
15 rt2660 ds2660-00 september 2015 www.richtek.com ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk 1 v v v v i i out in in out out(max) rms ? ? ? ? ? ? ? ? ? ? ? ? out l out 8fc 1 esr i v out out l in vv i = 1 fl v ??? ? ??? ??? ? ? ??? ? out out l(max) in(max) vv l = 1 fi v ??? ? ?? ??? ? ?? ??? ? having a lower ripple current reduces not only the esr losses in the output capacitors but also the output voltage ripple. however, it requires a large inductor to achieve this goal. for the ripple current selection, the val ue of i l = 0.4(i max ) will be a reasonable starting point. the large st ripple current occurs at the highest v in . to guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : the inductor's current rating (caused a 40 c temperature rising from 25 c ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. c in and c out selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the top mosfet. to prevent large ripple voltage, a low esr input capacitor sized for the maximum rms current should be used. rms current is given by : inductor selection the inductor value and operating frequency determine the ripple current according to a specific input and output voltage. the ripple current i l increases with higher v in and decreases with higher inductance. capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by : using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v dd . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. stability considerations setting the crossover frequency should be less than 1/5 of the switching frequency . choose r c value of 3.9k . then determine c c , using the below equation : to calculate c c = 3.4nf, choose the capacitor value of 2.2nf. then determine c p , set the pole more than the switching frequency, using the below equation : choose the c p to 33pf. p cs 11 c34pf 2 r 2f 2 3.9k 2 600khz ? ?? ? ?? ? ??? co z cc f1 f 52rc ? ?? ?? c 60khz 53m 160 f23.14 so r 3.2k 1000 s ??? ?? ??? c co out s 1gmr f60khz 2c r ? ?? ? ? sout r 53m , gm 1000 a/v, c 160 f ??? ? where
16 rt2660 www.richtek.com ds2660-00 september 2015 ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 9. derating curve of maximum power dissipation thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for vqfn-20l 3.5x4 packages, the thermal resistance, ja , is 32 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (32 c/w) = 3.125w for vqfn-20l 3.5x4 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 9 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. layout considerations follow the pcb layout guidelines for optimal performance of rt2660. ? a ground plane is recommended. if a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the gnd pin at one point that is then connected to the pgnd pin close to the ic. the exposed pad should be connected to gnd. ? connect the terminal of the input capacitor(s), c in , as close as possible to the vin pin. this capacitor provides the ac current into the internal power mosfets. ? sw node is with high frequency voltage swing and should be kept within small area. keep all sensitive small-signal nodes away from the sw node to prevent stray capacitive noise pick-up. ? flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
17 rt2660 ds2660-00 september 2015 www.richtek.com ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 10. pcb layout guide table 2. inductors pgnd pgnd pgnd vin vin gnd vref comp vout refin sw sw sw sw sw en v5in pgood mode boot pgnd 21 16 20 17 18 19 10 9 8 7 6 11 12 13 14 15 1 2 5 4 3 c in gnd v in r1 c comp r2 r comp c v5in v out pgnd c boot l sw should be connected to inductor by wide and short trace. keep sensitive components away from this trace the feedback and must be connected as close to the device as possible. keep sensitive component away. input capacitor must be placed as close to the ic as possible. gnd c out v out recommended component selection for typical application. component supplier series inductance ( ? h) dcr (m ? ) current rating (a) dimensions (mm) tdk spm5030t-r35 0.35 2.1 14.9 5x5x3 pulse pa2509.201nl 0.2 0.35 32 7x8.5x8 we 744308025 0.25 0.37 25 7x10x6.8
18 rt2660 www.richtek.com ds2660-00 september 2015 richtek technology corporation 14f, no. 8, tai yuen 1 st street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension v-type 20l qfn 3.5x4 package min. max. min. max. a 0.800 1.000 0.031 0.039 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 d 3.400 3.600 0.134 0.142 d2 2.050 2.150 0.081 0.085 e 3.900 4.100 0.154 0.161 e2 2.550 2.650 0.100 0.104 e l 0.350 0.450 0.014 0.018 symbol dimensions in millimeters dimensions in inches 0.500 0.020 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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